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Hardware acceleration in NFV applications promotes the processing performance of media plane

19 Mar 2019
00:00
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NFV, the virtualization of telecommunications network functions, reduces the cost of expensive network equipment by using the general COTS hardware (such as x86) and virtualization technologies to carry the software processing of network functions. NFV can, through software and hardware decoupling and functional abstraction, enable network device functions to no longer depend on dedicated hardware so that resources can be fully flexibly shared, rapid development and deployment of new services can be realized, and automatic deployment, elastic scaling, failure isolation and self-healing are based on actual service requirements. The NFV architecture, which is regarded as the latest communication network architecture defined by ETSI, will be doomed to be the choice of the new 5G network. At the same time, for the inventory network capacity of the existing network, its network architecture is transformed, for example, when C-plane and U-plane of the 4G network are deployed respectively, the NFV architecture is also adopted as usual.

However, the development of technology, like the development of history, always spirals upward. NFV has just evolved from professional hardware to general hardware. When it comes to 5G network applications and 4G network C/U-plane separation applications, it is found that COTS hardware represented mainly by X86 servers cannot meet the network performance requirements of 5G and 4G C/U-plane separation. There are two main reasons for this problem:

First, the general X86 CPU guarantees generality and loses its specificity, so it is not good at specific task processing, including parallel task processing such as audio/video encoding/decoding, message forwarding, and encryption and decryption.

Second, the performance of the X86’s general processor can no longer grow according to Moore's Law, and the telecom business characteristics have higher performance requirements than the increase speed of "Moore's Law".

In terms of the 5G network, to meet the large bandwidth and low latency of the 5G network, 5G RAN and 5G CORE have very large performance improvement requirements. It is difficult to meet the performance of X86 processors only; MECs located at edge DCs are subject to the limit of factors of the equipment room such as space, heat dissipation, and cost. Therefore, it is difficult to meet the requirements of high performance computing by using a pure X86 processor.

In terms of 4G C/U-plane separation, the U-plane has a high requirement for the forwarding throughput of packets, and the general X86 processor is not professional in packet forwarding.

In the 4G C/U-plane separation and 5G network application scenarios, because the general hardware used by NFV is defective in the performance or cost of specific task processing, the X86 processor is equipped with coprocessors (accelerator cards) such as FGPA and GPU. The solution re-appears in the NFV architecture. The telecommunications network has also undergone a spiral development process from "dedicated hardware -> general COTS hardware -> general COTS hardware + dedicated accelerator card hardware". The latest ETSI NFV architecture also introduces hardware acceleration into the NFV architecture, as shown in the following figure:

Figure 1 NFV Reference Architecture

In the new VNF architecture, NFVI has been enhanced to increase the capabilities to accelerate resource virtualization, including abstracting the accelerator, presenting it in a logical acceleration of resources, and providing comprehensive acceleration services uniformly. The virtualization layer provides a unified interface for adapting to different forms of acceleration devices such as accelerators.

Current development of the hardware acceleration solution in NFV
The current status of hardware acceleration solutions mainly includes the status of hardware acceleration research in standard and open source organizations, and the application status of hardware acceleration solutions.

First of all, for the status of hardware acceleration research in standard and open source organizations, here are two major research (open source) organizations – ETSI and OpenStack.

In addition to the hardware acceleration module function in the NFV architecture, ETSI also defines two implementation solutions of hardware acceleration: the pass-through solution and the abstract model solution.

  • Pass-through solution: It is the PCI/PCIe-pass-through solution, which directly passes the hardware acceleration card on the PCI slot to a specific virtual machine. The pass-through solution is currently the most general solution. Its disadvantage is that the hardware is monopolized by the virtual machine, and the upper layer application or the virtual machine needs to maintain the hardware drivers of different acceleration cards.
  • Abstract model solution. In the NFVI or Hypervisor, you can maintain the "Backend/HW Driver" module; at the VNF layer, you can maintain the "Generic Driver" module in the VNFC; the NFVI is responsible for the acceleration card scanning and driver loading, and the virtualization management of the acceleration card hardware, and mounting the virtual accelerator card to the virtual machine. Its advantages include that an accelerator card resource can be used by multiple virtual machines, acceleration resources can be loaded or released; the VM uses only one general acceleration card driving program for various accelerator cards, and the maintenance of virtual machines is simple.

While ETSI defines the hardware acceleration framework and implementation, the open source community OpenStack also launches the Cyborg project. Its main goal is to manage the installation drivers, dependencies, and installation and uninstallation of various accelerators. The accelerators and virtual instances that are created by the accelerator and Nova can be connected, which are designed to provide a common hardware acceleration management framework. OpenStack is primarily aimed at the integration of drivers of accelerated hardware in the infrastructure and VIM's perception of accelerated hardware, without involving the upper-layer MANO. At present, the Cyborg project is still a framework and has no valid codes yet. ZTE actively participates in the tasks from the OpenStack Cyborg community and is mainly engaged in the development of Cyborg Driver to support future high-precision clock synchronization cards for 5G, MEC and other high reliability and low latency scenarios. At the same time, as a sub-team leader of the Cyborg, ZTE actively participates in the related work of the Cyborg documentation team.

From the introduction of the acceleration solutions made by the above standard and open source communities, it can be seen that the current hardware acceleration solutions, especially the hardware acceleration abstract solutions, are not mature yet. At the same time, the use of the acceleration hardware involves the cooperation and linkage of accelerator card manufacturers, cloud platform manufacturers and network element manufacturers. This needs to be targeted at the corresponding accelerator card products to make integration drive and virtualization of these products at the cloud platform layer, provide the corresponding acceleration library or SDK, and call the network element layer.

The application status of the hardware acceleration solution in NFV can be summarized as follows:

  • The usage mode is simple. The current main usage mode is to use the corresponding acceleration hardware for the VM pass-through. The hardware accelerator card cannot be flexibly used or shared between multiple VMs, resulting in unbalanced resource utilization.
  • The general acceleration hardware or interfaces are not standardized. Each hardware manufacturer's acceleration chip is a specific acceleration driver. The SDK provided by the cloud platform manufacturer has a large difference, and the network element layer needs to be adapted and customized for development, and the degree of standardization is low.
  • It is necessary to expand MANO. The use of hardware acceleration can be divided into four stages: perception, allocation, scheduling, and release. Perception requires the cloud platform to identify and allocate hardware types. Allocation requires the VNFM and NFVO to support network elements to resolve the requests for acceleration hardware resources. Scheduling requires the cloud platform to monitor and deploy the acceleration resources. Release requires the cloud platform to reprogram the accelerated hardware resources. These applications all need to expand MANO.


ZTE NFV hardware acceleration solution
As a leading global integrated communications solution provider, ZTE is a leader in the 5G industry. Hardware acceleration is an important solution to improve network performance in the 5G network. ZTE actively participates in hardware acceleration standards and solutions of ETSI and OpenStack. Meanwhile, it has launched its own hardware acceleration solution. The architecture of ZTE's hardware acceleration solution is shown in the following figure:

Figure 2 Virtualization Management and Applications of Hardware Accelerations

The ZTE hardware acceleration solution has the following advantages:

  • The compute node is the most important one for virtualization management of accelerator cards. It provides the following capabilities:

• Through the FPGA or GPU driver, it discovers the hardware acceleration board, records the hardware acceleration capability (set), integrates the driver as a general driver, and reports the capability to VIM;

• It generates virtual machines with specific acceleration capabilities, loads corresponding acceleration hardware, and provides front-end drivers of general virtual machine.

  • The VIM node mainly manages the acceleration capability of the compute nodes, reports the acceleration capability to NFVM/NFVO or other application orchestrators such as HEAT, and completes the deployment of the virtual machine with acceleration capability.


The ZTE hardware acceleration solution currently supports FPGA-based GTP service acceleration, GPU-based video/audio service acceleration and QAT encryption and decryption acceleration.

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